module xu_lie_gen(clk, din, dout,rst);  
 
 input clk,rst;  
 input [3:0] din;  
 output reg dout;    
 reg[3:0] temp;
 reg tpm = 0;
 always @(posedge clk) begin
	if (rst) begin
		dout = 0;
		tpm = 0;
	end
	else begin
			if (tpm==0) begin
				temp = din;
				tpm = 1;
			end
			dout = temp[3];
         temp = temp<<1;    
			temp[0] = dout;
	end
end  
 
endmodule
